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general description the ds1870 is a dual-channel bias controller targeted toward class ab ldmos rf power-amplifier applica- tions. it uses lookup tables (luts) to control 256-posi- tion potentiometers based on the amplifier? temperature and drain voltage or current (or other external monitored signal). with its internal temperature sensor and multichannel a/d converter (adc), the ds1870 provides a cost-effective solution that improves the amplifier? efficiency by using nonlinear compensa- tion schemes that are not possible with conventional biasing solutions. applications cellular base stations medical equipment industrial controls optical transceivers features ? two-channel solution for programmable rf bias control ? the potentiometers position is automatically updated to compensate for the ambient temperature and the drain voltage or current ? a five-channel, 13-bit adc continuously monitors the ambient temperature, v cc , v d , i d1, and i d2 ? hi/lo alarms for each adc channel can trigger a fault output ? nonvolatile memory for the device settings, lookup tables, and 32-bytes of user memory ? i 2 c*-compatible serial interface with up to eight devices on the same serial bus ? single 5v power supply ? small 16-pin tssop package ? -40c to +95c operational temperature range ds1870 ldmos rf power-amplifier bias controller ______________________________________________ maxim integrated products 1 tssop (173 mils) 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 l 1 top view w 1 w 2 l 2 i d1 i d2 v d gnd fault a 0 a 1 a 2 scl sda h com v cc ds1870 pin configuration ordering information rev 2; 2/06 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package ds1870e-010 -40? to +95? 16 tssop (173 mils) ds1870e-010+ -40? to +95? 16 tssop (173 mils) + denotes lead-free package. typical operating circuit appears at end of data sheet. *purchase of i 2 c components of maxim integrated products, inc., or one of its sublicensed associated companies, conveys a license under the philips i 2 c patent rights to use these com- ponents in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips.
ds1870 ldmos rf power-amplifier bias controller 2 _____________________________________________________________________ absolute maximum ratings recommended dc operating conditions (t a = -40? to +95?) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on v cc , h com , sda, and scl pins relative to ground ...............................................................-0.5v to +6.0v voltage range on a 0 , a 1 , a 2 , fault, v d , i d1 , i d2 relative to ground. ...................-0.5v to v cc + 0.5v, not to exceed +6.0v voltage range on l0, l1, w0, and w1 relative to ground .................-0.5v to h com + 0.5v, not to exceed +6.0v operating temperature range ...........................-40? to +95? eeprom programming temperature range .........0? to +70? storage temperature range .............................-55? to +125? soldering temperature .......................................see ipc/jedec j-std-020a specification parameter symbol conditions min typ max units supply voltage v cc (note 1) 4.5 5.5 v input logic 1 (sda, scl, a 2 , a 1 , a 0 ) v ih 0.7 x v cc v cc + 0.3 v input logic 0 (sda, scl, a 2 , a 1 , a 0 ) v il -0.3 +0.3 x v cc v h com voltage 4.5 5.5 v l x and w x voltage -0.3 h com + 0.3 v wiper current -1 +1 ma dc electrical characteristics (v cc = +4.5 to 5.5v, t a = -40? to +95?.) parameter symbol conditions min typ max units supply current i cc (note 2) 1 2 ma input leakage i li -200 +200 na v ol1 3ma sink current 0.4 v low-level output voltage (sda, fault) v ol2 6ma sink current 0.6 v i/o capacitance c i/o 10 pf digital power-on reset v pod 1.0 2.2 v analog power-on reset v poa 2.0 2.8 v
ds1870 ldmos rf power-amplifier bias controller _____________________________________________________________________ 3 analog voltage-monitoring characteristics (v cc = +4.5 to 5.5v, t a = -40? to +95?.) parameter symbol conditions min typ max units v d monitor factory- calibrated fs code fff8h 2.488 2.500 2.513 v v cc monitor factory- calibrated fs code fff8h 6.521 6.553 6.587 v i d1 and i d2 monitor factory- calibrated fs code fff8h 0.4975 0.5000 0.5025 v resolution (v cc , v d , i d1 , i d2 ) 0.0122 %fs accuracy (v cc , v d , i d1 , i d2 ) 0.25 0.5 %fs update rate for v cc , v d , i d1 , i d2 t frame 50 ms digital thermometer characteristics (v cc = +4.5 to 5.5v, t a = -40? to +95?.) parameter symbol conditions min typ max units thermometer error t err -40? to 95? -3 +3 ? update rate t frame 50 ms analog potentiometer characteristics (v cc = +4.5 to 5.5v, t a = -40? to +95?.) parameter symbol conditions min typ max units wiper resistance +25? 500 1000 potentiometer end-to-end resistance r pot +25? 10.0 13 16.8 k resolution 0.4 %fs absolute linearity (note 3) -1 +1 lsb relative linearity (note 4) -0.5 +0.5 lsb ratiometric temperature coefficient 5 ppm/? end-to-end temperature coefficient 70 ppm/? -3db cutoff frequency (note 5) 1 mhz series resistors from l1, l2 to gnd r s +25? 15.1 19.5 25.2 k v hcom /v lx 0.5975 0.6 0.6025
ds1870 ldmos rf power-amplifier bias controller 4 _____________________________________________________________________ lookup table characteristics (v cc = +4.5 to 5.5v, t a = -40? to +95?.) parameter symbol conditions min typ max units pot1 and pot2 temp lut size 72 bytes each pot1 and pot2 temp lut index range -40 +102 ? temp step 2c temp hysteresis (note 6) 1 c pot1 and pot2 drain lut size 64 bytes each pot1 and pot2 drain lut v d index range 8000 fe00 hex pot1 and pot2 drain lut v d step 0200 hex pot1 and pot2 drain lut v d hysteresis (note 6) 0100 hex pot1 and pot2 drain lut i dx index range 0000 7e00 hex pot1 and pot2 drain lut i dx step 0200 hex pot1 and pot2 drain lut i dx hysteresis (note 6) 0100 hex
ds1870 ldmos rf power-amplifier bias controller _____________________________________________________________________ 5 ac electrical characteristics (v cc = +4.5v to 5.5v, t a = -40? to +95?, timing referenced to v il(max) and v ih(min) .) (figure 3) parameter symbol conditions min typ max units scl clock frequency f scl (note 7) 0 400 khz bus free time between stop and start conditions t buf 1.3 ? hold time (repeated) start condition t hd:sta 0.6 ? low period of scl t low 1.3 ? high period of scl t high 0.6 ? data hold time t hd:dat 0 0.9 ? data setup time t su:dat 100 ns start setup time t su:sta 0.6 ? sda and scl rise time t r (note 8) 20 + 0.1c b 300 ns sda and scl fall time t f (note 8) 20 + 0.1c b 300 ns stop setup time t su:sto 0.6 ? sda and scl capacitive loading c b (note 8) 400 pf eeprom write time t w (note 9) 10 20 ms nonvolatile memory characteristics (v cc = +4.5v to 5.5v, t a = 0? to +70?.) parameter symbol conditions min typ max units writes +70? (note 5) 50,000 note 1: all voltages referenced to ground. note 2: supply current is measured with all logic inputs at their inactive state (sda = scl = v cc ) and driven to well-defined logic levels. all outputs are disconnected. note 3: absolute linearity is the difference of measured value from expected value at the dac position. expected value is a straight line from measured minimum position to measured maximum position. note 4: relative linearity is the deviation of an lsb dac setting change vs. the expected lsb change. expected lsb change is the slope of the straight line from measured minimum position to measured maximum position. note 5: this parameter is guaranteed by design. note 6: see figure 1. note 7: i 2 c interface timing shown is for fast-mode (400khz) operation. this device is also backward compatible with i 2 c stan- dard-mode timing. note 8: c b ?otal capacitance of one bus line in picofarads. note 9: eeprom write begins after a stop condition occurs.
ds1870 ldmos rf power-amplifier bias controller 6 _____________________________________________________________________ typical operating characteristics (v cc = +5.0v, t a = +25?, unless otherwise noted.) potentiometer 1 and 2 output voltage vs. positon ds1870 toc04 wiper position (dec) wiper voltage (v) 192 128 64 1 2 3 4 5 6 0 0 256 h com = 5v l1 and l2 not connected potentiometer 1 differential nonlinearity vs. wiper position ds1870 toc05 wiper position (dec) differential nonlinearity (lsb) 192 128 64 -0.20 -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0.20 0.25 -0.25 0 256 potentiometer 2 differential nonlinearity vs. wiper position ds1870 toc06 wiper position (dec) differential nonlinearity (lsb) 192 128 64 -0.20 -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0.20 0.25 -0.25 0 256 potentiometer 1 integral nonlinearity vs. wiper position ds1870 toc07 wiper position (dec) integral nonlinearity (lsb) 192 128 64 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 256 potentiometer 2 integral nonlinearity vs. wiper position ds1870 toc08 wiper position (dec) integral nonlinearity (lsb) 192 128 64 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 256 potentiometer 1 and 2 wiper resistance vs. wiper voltage ds1870 toc09 wiper voltage (v) wiper resistance ( ) 4 3 2 1 100 200 300 400 500 600 700 800 900 1000 0 05 h com = 5.0v supply current vs. supply voltage ds1870 toc01 supply voltage (v) supply current ( a) 5.3 5.1 4.9 4.7 620 640 660 680 700 720 740 760 780 800 600 4.5 5.5 supply current vs. temperature ds1870 toc02 temperature ( c) supply current ( a) 80 60 20 40 0 -20 450 500 550 600 650 700 750 800 850 900 400 -40 100 v cc = 5.5v v cc = 4.5v v cc = 5.0v h com current vs. h com voltage ds1870 toc03 h com voltage (v) h com current (ma) 5.3 5.1 4.9 4.7 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0 4.5 5.5
ds1870 ldmos rf power-amplifier bias controller _____________________________________________________________________ 7 typical operating characteristics (continued) (v cc = +5.0v, t a = +25?, unless otherwise noted.) output drift (ppm/c) -15 -10 -5 0 5 10 15 20 -20 potentiometer low terminal voltage vs. temperature ds1870 toc12 temperature ( c) 80 60 -20 0 20 40 -40 100 l1 l2 h com = 5.0v v cc conversion error vs. supply voltage ds1870 toc13 supply voltage (v) error (% fs) 5.0 4.5 4.0 3.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 3.0 5.5 default v cc calibration vd conversion error vs. input voltage ds1870 toc14 input voltage (v) error (% fs) 2.0 1.5 1.0 0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 2.5 default vd calibration id1 conversion error vs. input voltage ds1870 toc15 input voltage (v) error (% fs) 0.4 0.3 0.2 0.1 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 0.5 default id1 calibration id2 conversion error vs. input voltage ds1870 toc16 input voltage (v) error (% fs) 0.4 0.3 0.2 0.1 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 0.5 default id2 calibration potentiometer 1 and 2 wiper resistance vs. wiper voltage ds1870 toc09 wiper voltage (v) wiper resistance ( ) 4 3 2 1 100 200 300 400 500 600 700 800 900 1000 0 05 h com = 5.0v potentiometer 1 and 2 wiper resistance vs. temperature ds1870 toc10 temperature ( c) resistance change from 25 c (ppm/c) 80 60 20 40 0 -20 100 200 300 400 500 600 700 800 900 1000 0 -40 100 h com = 5v wiper voltage = 4v potentiometer end-to-end resistance vs. temperature ds1870 toc11 temperature ( c) change from resistance at 25 c (ppm/c) 80 60 -20 0 20 40 -150 -100 -50 0 50 100 150 200 -200 -40 100 r pot2 + r s2 r pot1 + r s1
ds1870 ldmos rf power-amplifier bias controller 8 _____________________________________________________________________ pin description pin name function 1l 1 potentiometer 1 low terminal 2w 1 potentiometer 1 wiper terminal 3w 2 potentiometer 2 wiper terminal 4l 2 potentiometer 2 low terminal 5i d1 drain current 1 monitor input 6i d2 drain current 2 monitor input 7v d drain voltage monitor input 8 gnd ground 9 fault fault output. this open-collector output is active high when one of the enabled alarms is outside its programmable limit value. 10 a 0 11 a 1 12 a 2 i 2 c address inputs. these inputs determine the slave address of the device. the slave address in binary is 1010a 2 a 1 a 0 . 13 scl serial clock input. i 2 c clock input. 14 sda serial data input/output. bidirectional i 2 c data pin. 15 h com potentiometer high terminal. common to potentiometers 1 and 2. 16 v cc power input
ds1870 ldmos rf power-amplifier bias controller _____________________________________________________________________ 9 functional diagram + + + + + + m u x 13-bit adc on-chip temp sensor v cc v d i d1 i d2 address generation sda scl a 0 a 1 a 2 i 2 c data bus 32 bytes user memory offset calibration registers fault load index index index index load temp pot1 r pot pot2 r pot h com l 2 w 2 w 1 l 1 pot1 drain lut table 4 (64 bytes) pot2 drain lut table 5 (64 bytes) limit comparator limit flag registers fault mask v cc v cc gnd gain calibration registers v d vd1 vd2 v d i d2 i d1 pot1 temp lut table 2 (72 bytes) pot2 temp lut table 3 (72 bytes) r s r s i 2 c interface control hi and lo limits for temp, v cc , v d , i d1 , i d2 measured values for temp, v cc , v d , i d0 , i d1 ds1870
ds1870 ldmos rf power-amplifier bias controller 10 ____________________________________________________________________ detailed description the ds1870 is a dual-channel ldmos bias controller. it is intended to replace traditional bias control solu- tions that are limited by a constant temperature-coeffi- cient correction. this ic offers lookup table correction that is programmable as a function of temperature as well as drain supply voltage or current. the flexibility to use a nonlinear bias correction improves efficiency sig- nificantly. this is a direct consequence of the ability to lower the bias current, particularly in class ab opera- tion, since the bias correction no longer requires a con- stant temperature coefficient. in addition, correcting the bias as a function of drain supply voltage, or drain cur- rent in class ab, assists in distortion reduction and gain management. two outputs (w1 and w2), each controlled by a dedi- cated two-dimensional lookup table as shown in the functional diagram, drive two ldmos gates. the two degrees of freedom are temperature and either drain supply voltage or drain current. the lookup tables are programmed during power-amplifier assembly and test. after calibration, the ic automatically recalls the proper control setting for each output, based on tem- perature and drain characteristics. a 13-bit adc samples and digitizes the chip tempera- ture, v cc , the drain supply voltage, and two drain cur- rents. these digitized signals are stored in memory ready to be accessed by the look up table controls. the digitized values are also compared to alarm thresholds generating high or low alarm flags. the fault output can be configured to assert high based any alarm? assertion, or the alarms can be masked to prevent unwanted fault assertions. the adc readings as well as the alarm flags and fault status are accessi- ble through the i 2 c-compatible interface. voltage/current monitor operation the ds1870 monitors four voltages (v cc , v d , i d1 , and i d2 ) plus the temperature in a round-robin fashion using its 13-bit adc. the converted voltage values are stored in memory addresses 62h?9h as 16-bit unsigned numbers with the adc result left justified in the register. the three least significant bits of the adc result registers are masked to zero. the round-robin time is specified by t frame in the analog voltage-monitoring characteristics. the default factory-calibrated values for the voltage monitors are shown in table 1. to calculate the voltage measured from the register value, first calculate the lsb weight of the 16-bit regis- ter that is equal to the full-scale voltage span divided by 65,528. next, convert the hexadecimal register value to decimal and multiply it times the lsb weight. example: using the factory default v cc trim, what volt- age is measured if the v cc register value is c347h? the lsb for v cc is equal to (6.553v - 0v) / 65,528 = 100.00?. c347h is equal to 49,991 decimal, which yields a supply voltage equal to 49,991 x 100.00? = 4.999v. table 2 shows more conversion examples based on the factory trimmed adc settings. by using the internal gain and offset calibration regis- ters, the +fs and -fs signal values shown in table 1 can be modified to meet customer needs. for more information on calibration, see the voltage-monitor calibration section. note: the method shown above for determining the input voltage level only works when the offset register is set to zero. signal +fs signal +fs (hex) -fs signal -fs (hex) v cc 6.553v fff8 0v 0000 v d 2.5v fff8 0v 0000 i d1 0.5v fff8 0v 0000 i d2 0.5v fff8 0v 0000 table 1. voltage-monitor factory default calibration signal lsb weight (?) register value (hex) input voltage (v) v cc 100.00 8080 3.29 v cc 100.00 c0f8 4.94 v d 38.152 c000 1.875 v d 38.152 8080 1.255 i d1 7.6303 8000 0.2500 i d2 7.6303 1328 0.0374 table 2. voltage-monitor conversion examples
ds1870 ldmos rf power-amplifier bias controller ____________________________________________________________________ 11 temperature-monitor operation the internal temperature monitor values are stored as 16-bit 2? complement numbers at memory addresses 60h to 61h. the round-robin update time (t frame ) for the temperature register is the same as the voltage moni- tors. the factory default calibration values for the tem- perature monitor are shown in table 3. to convert the 2? complement register value to the temperature it represents, first convert the 2-byte hexa- decimal value to a decimal value as if it is an unsigned value, then divide the result by 256. finally, subtract 256 if the result of the division is greater than or equal to +128. table 4 shows example converted values. the offset of the temperature sensor can be adjusted using the internal calibration registers to account for differences between the ambient temperature at the location of the ds1870 and the temperature of the device it is biasing. when offsets are applied to the temperature measurement, the value converted will be off by a fixed value from the ds1870? ambient temper- ature. for more information, see the temperature monitor offset calibration section. potentiometer operation both of the ds1870? potentiometers are 256 positions with their high terminals connected to the high common pin, h com . the low terminals of the potentiometers are internally shunted to gnd by resistors such that the output voltage is 3v to 5v when h com is connected to a 5v source. the internal shunt resistors and the poten- tiometer? end-to-end resistance feature matching tem- perature coefficients that prevent the output voltage from drifting over temperature. external resistors can be placed from h com to l x and/or from l x to gnd to modify the typical output voltage. normal operation during normal operation, each potentiometer? position is automatically adjusted to the sum of its temperature and drain lut values after each round of conversions. the potentiometer setting is applied after both the base and offset lut values are recalled from memory. the sum of the currently indexed values in the pot1 temp lut (memory table 2) and the pot1 drain lut (memo- ry table 4) control potentiometer 1. the sum of the cur- rently indexed values in the pot2 temp lut (memory table 3) and the pot2 drain lut (memory table 5) con- trol potentiometer 2. in the event that two table values are summed and the result is greater than 255 or less than 0, the potentiometer? position is set to 255 or 0, respectively. signal +fs signal +fs (hex) -fs signal -fs (hex) temp +127.97? 7ff8 -128.00? 8000 table 3. internal temperature-monitor factory default calibration msb (bin) lsb (bin) temperature (?) 01000000 00000000 +64 01000000 00001111 +64.059 01011111 00000000 +95 11110110 00000000 -10 11011000 00000000 -40 table 4. temperature conversion values lut address (hex) corresponding temperature (?) 80 -40? 81 -38? 82 -36? c6 +100? c7 +102? table 5. lut addresses for corresponding temperature values
ds1870 ldmos rf power-amplifier bias controller 12 ____________________________________________________________________ the temperature tables (lut 2 and lut 3) are 72 bytes each. this allows the biasing to be adjusted every 2? between -40? and +102?. temperatures less than -40? or greater than +102? use the -40? or +102? values, respectively. the values in the temperature tables are 8-bit unsigned values (0 to 255 decimal) that allow the potentiometer to be set to any position as a function of the temperature. the temperature luts have 1? hysteresis (figure 1) to prevent the poten- tiometer? position from chattering in the event the tem- perature remains near a lut switching point. table 5 shows how the ds1870 determines the temperature tables index as a function of temperature. the drain tables (lut 4 and lut5) are 64 bytes each, and they can be indexed either by the drain voltage or the drain current corresponding to the potentiometer. the vd1 control bit determines if the voltage sensed on v d or i d1 adjusts the pot1 drain lut, and the vd2 control bit determines if the voltage sensed on v d or i d2 controls the pot2 drain lut. the vd1 and vd2 control bits are located in register 85h of memory table 1. the drain tables are programmed with an 8-bit signed value (-128 to +127 decimal) that allow a rela- tive offset from the temperature lut values determined by the amplifier? drain characteristics. the drain luts are indexed either by the upper half of the v d range or the lower half of its corresponding i dx range. table 6 shows how the index is determined based on the v d or i dx values. hysteresis equal to 0100h is also implemented on the drain monitor (figure 1) to ensure that voltages close to a switching point do not cause the potentiometer position to chatter between two lut values. the drain lut index values are specified in hexadecimal because the hexadecimal val- ues are applicable regardless of the gain and offset cali- bration of the ds1870. manual mode during normal operation, the potentiometer position is automatically modified once per conversion cycle based on the adc results. the ds1870 can either stop the update function all together by using the b/o_en bit, or the temperature and drain lut indexes can be manually controlled by using the index_en bit. these bits are located in the man dac register located in memory table 1, byte afh. more information about these bits is in the register description section. voltage-monitor calibration the ds1870 can scale each analog voltage? gain and offset to produce the desired digital result. each of the inputs (v cc , v d , i d1 , i d2 ) has a unique register for the gain and offset (in memory table 1) allowing them to be individually calibrated. additionally, the ds1870 offers the ability to provide a temperature offset to allow the temperature measurement to be compensated to account for the difference in temperature between the ds1870 and the device it is biasing. to scale the gain and offset of the converter for a spe- cific input, you must first know the relationship between the analog input and the expected digital result. the input that would produce a digital result of all zeros is the null value (normally this input is gnd). the input that would produce a digital result of all ones (fff8h) is lut address (hex) v d value (hex) i dx value (hex) 80 8000 0000 81 8200 0200 82 8400 0400 be fc00 7c00 bf fe00 7e00 table 6. lut addresses for v d or i dx values 9ah 99h 98h 97h 96h 95h 2 4 6 8 10 12 temperature ( c) memory location memory location memory location 9ah 99h 98h 97h 96h 95h aa00 ac00 aeoo b000 b200 b400 drain voltage conversion (hex) 9ah 99h 98h 97h 96h 95h 2a00 2c00 2e00 3000 3200 3400 drain current conversion (hex) increasing temperature increasing drain voltage increasing drain current decreasing temperature decreasing drain voltage decreasing drain current figure 1. lut hysteresis
ds1870 ldmos rf power-amplifier bias controller ____________________________________________________________________ 13 the full-scale (fs) value. the expected fs value is also found by multiplying an all-ones digital answer by the lsb weight. example: since the fs digital reading is 65,528 (fff8 hex) lsbs, if the lsb? weight is 50?, then the fs value is 65,528 x 50? = 3.2764v. a binary search is used to calibrate the gain of the con- verter. this requires forcing two known voltages to the input pin. it is preferred that one of the forced voltages is the null input and the other is 90% of fs. since the lsb of the least significant bit in the digital reading reg- ister is known, the expected digital results can be cal- culated for both the null input and the 90% of full scale value. an explanation of the binary search used to scale the gain is best served with the following example pseudo- code: /* assume that the null input is 0.5v */ /* assume that the requirement for the lsb is 50? */ fs = 65528 * 50e-6; /*3.2764v */ cnt1 = 0.5 / 50e-6; /* 1000 */ cnt2 = 0.9 x fs / 50e-6; /* 58981.5 */ /* so the null input is 0.5v and 90% of fs is 2.949v */ set the input? offset register to zero gain_result = 0h; /* working register for gain calculation */ clamp = fff8h; /* this is the max adc value*/ for n = 15 down to 0 begin gain_result = gain_result + 2 n ; write gain_result to the input? gain register; force the 90% fs input (2.949v); meas2= adc result from ds1870; if meas2 clamp then gain_result = gain_result - 2 n ; else force the null input (0.5v) meas1 = adc result from ds1870 if [(meas2-meas1)>(cnt2-cnt1)] then gain_result = gain_result - 2 n ; end; write gain_result to the input? gain register; the gain register is now set and the resolution of the conversion matches the expected lsb. customers requiring non-zero null values (e.g., 0.5v) must next calibrate the input? offset. if the desired null value is 0v, leave the offset register programmed to 0000h and skip this step. to calibrate the offset register, program the gain regis- ter with the gain_result value determined above. next, force the null input voltage (0.5v for the example) and read the digital result from the part (meas1). the offset value can be calculated using the following formula: temperature-monitor offset calibration the ds1870? temperature sensor comes precalibrated and requires no further adjustment by the customer for proper operation. however, it is possible for customers to characterize their system and add a fixed offset to the ds1870? temperature reading so it is reflective of another location? temperature. this is not required for biasing because the temperature offset can be accounted for by adjusting the data? location in the luts, but this feature is available for customers who see application benefits. to change the temperature sensor? offset: write the temperature offset register to 0000h, measure the source reference temperature (t ref ), and read the tem- perature from the ds1870 (t ds1870 ). then, the follow- ing formula can be used to calculate the value for the temperature offset register. once the value is calculated, write it to the temperature offset register. power-up and low-voltage operation during power-up, the device is inactive until v cc exceeds the digital power-on-reset voltage (v pod ). at this voltage, the digital circuitry, which includes the i 2 c- compatible interface, becomes functional. however, eeprom-backed registers/settings cannot be internally read (recalled) until v cc exceeds the analog power-on reset (v poa ), at which time the remainder or the device becomes fully functional. once v cc exceeds v poa , the rdyb bit in byte 74h is timed to go from a 1 to a 0 and indicates when adc conversions begin. if v cc ever dips below v poa , the rdyb bit reads as a 1 again. once a device exceeds v poa and the eeprom is recalled, the values remain active (recalled) until v cc falls below v pod . tempoffset t t xor bb h ref ds bitwise =?+ ? () () 64 275 40 1870 offset meas =? ? ? ? ? ? ? 1 1 4
ds1870 ldmos rf power-amplifier bias controller 14 ____________________________________________________________________ as the device powers up, the v cc lo alarm flag defaults to a 1 until the first v cc adc conversion occurs and sets or clears the flag accordingly. the fault output is active when v cc < v poa . memory description the ds1870 memory map is divided into six sections that include the lower memory (addresses 00h to 7fh) and five memory tables (figure 2). the memory tables are addressed by setting the table-select byte (7fh) to the desired table number and accessing the upper memory locations (80h to ffh). the lower memory can be addressed at any time regardless of the state of the table-select byte. the lower memory and memory table 1 are used to configure the ds1870 and read the status of the monitors. the lower memory also contains the 32 bytes of user memory. memory tables 2 and 3 contain the base potentiometer positions that are used for bias- ing based on the reading of the internal temperature sensor. memory tables 4 and 5 contain the relative off- sets that are added to the base number as a function of either the drain voltage or the individual drain current monitors. see the memory map for a complete listing of registers and the register description section for details about each register. password memory protection the ds1870 contains a 2-byte password that allows all of its ee memory to be write protected until the proper password is entered into the password entry (pwe) word (address 78h). this allows factory calibration data for the bias settings, alarm thresholds, and all the other eeprom information to be write protected. the pass- word is set by writing to the password register, which is the first two bytes of memory table 1. the factory default value for the password is ffffh, which is also the factory default value for pwe on power-up. this means that parts are unlocked at power-up when they are first received by customers. the password should be programmed to a value other than ffffh to ensure the calibration data is write pro- tected. the pwe register always reads 0000h regard- less of its programmed value. eeprom write disable memory locations 20h to 3fh and table 1 locations 80h to a7h are sram-shadowed eeprom. by default ( see = 0) these locations act as ordinary eeprom. by setting see = 1, these locations begin to function like sram cells, which allow an infinite number of write cycles without concern of wearing out the eeprom. this also eliminates the requirement for the eeprom write time. because changes made with see = 1 do not affect the eeprom, these changes are not retained through power cycles. the power-up value is the last value written with see = 0. this function can be used to limit the number of eeprom writes during calibration or to change the monitor thresholds periodically during normal operation without wearing out the eeprom. the see bit resides in memory table 1, byte afh. memory map the upper part of the memory map is organized into 8-byte or 4-word (2-byte) rows. the beginning address of the row is shown in the left-most column of the map, and is equal to the byte 0 or word 0 memory address. the next byte (byte 1) is located at the next highest memory address, and the next word (word 1) is two memory addresses greater than the row? beginning address. the lower part of the memory map expands the bytes or the words to show the names of the bits within the byte/word, or their bit weights (2 x ) for regis- ters that contain numerical information. numerical reg- isters that contain an ??in the most significant bit are showing sign extension for 2? complement numbers. descriptions of each byte/bit follow in the register description section. user memory; hi/lo alarm thresholds; adc results; configuration configuration pot1 temp lut pot2 temp lut pot1 drain lut pot2 drain lut 00h 7fh 80h afh 80h c7h 80h c7h 80h bfh 80h bfh main memory table 1 table 2 table 3 table 4 table 5 table-select byte (7fh) sel sel sel sel sel figure 2. memory organization
ds1870 ldmos rf power-amplifier bias controller ____________________________________________________________________ 15 lower memory word 0 word 1 word 2 word 3 row (hex) row name byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 00 user row 0 user ee user ee user ee user ee user ee user ee user ee user ee 08 user row 1 user ee user ee user ee user ee user ee user ee user ee user ee 10 user row 2 user ee user ee user ee user ee user ee user ee user ee user ee 18 user row 3 user ee user ee user ee user ee user ee user ee user ee user ee 20 threshold 0 temp hi alarm v cc hi alarm vd hi alarm id1 hi alarm 28 threshold 1 id2 hi alarm reserved reserved reserved 30 threshold 2 temp lo alarm v cc lo alarm vd lo alarm id1 lo alarm 38 threshold 3 id2 lo alarm reserved reserved reserved 40 reserved reserved reserved reserved reserved reserved reserved reserved 48 reserved reserved reserved reserved reserved reserved reserved reserved 50 reserved reserved reserved reserved reserved reserved reserved reserved 58 reserved reserved reserved reserved reserved reserved reserved reserved 60 a2d value 0 temp value v cc value vd value id1 value 68 a2d value 1 id2 value reserved reserved reserved 70 status hi alarm lo alarm reserved reserved i/o status a2d status reserved reserved 78 table select pwe reserved reserved reserved reserved reserved tbl sel expanded bytes bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte (hex) byte name bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00-1f user ee ee ee ee ee ee ee ee ee 20 temp hi alrm s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 22 v cc hi alrm 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 24 vd hi alrm 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 26 id1 hi alrm 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 28 id2 hi alrm 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 30 temp lo alrm s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 32 v cc lo alrm 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 34 vd lo alrm 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 36 id1 lo alrm 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 38 id2 lo alrm 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 60 temp value s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 62 v cc value 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 64 vd value 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 66 id1 value 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 68 id2 value 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 70 hi alarm temp hi v cc hi vd hi id1 hi id2 hi reserved reserved reserved 71 lo alarm temp lo v cc lo vd lo id1 lo id2 lo reserved reserved reserved 74 i/o status reserved reserved reserved reserved fault mint reserved rdyb 75 a2d status temp rdy v cc rdy vd rdy id1 rdy id2 rdy reserved reserved reserved 78 pwe 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 7f tbl sel 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0
ds1870 ldmos rf power-amplifier bias controller 16 ____________________________________________________________________ table 1 ( configuration ) word 0 word 1 word 2 word 3 row (hex) row name byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 80 config password lut sel fault ena reserved 88 scale 0 reserved vcc scale vd scale id1 scale 90 scale 1 id2 scale reserved reserved reserved 98 offset 0 reserved vcc offset vd offset id1 offset a0 offset 1 id2 offset reserved reserved temp offset a8 lut index t index o1 index o2 index pot1 base pot1 off pot2 base pot2 off man dac expanded bytes bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte (hex) byte name bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80 password 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 85 lut sel reserved reserved reserved reserved reserved reserved vd2 vd1 86 fault ena temp ena vcc ena vd ena id1 ena id2 ena reserved reserved reserved 8a vcc 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 8c vd scale 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 8e id1 scale 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 90 id2 scale 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 9a vcc offset ss2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 9c vd offset s s 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 9e id1 ss2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 a0 id2 ss2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 a6 temp offset s2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 a8 t index 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 a9 o1 index 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 aa o2 index 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 ab pot1 base 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 ac pot1 off s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 ad pot2 base 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 ae pot2 off s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 af man dac reserved reserved reserved reserved reserved see b/o_en index_en
ds1870 ldmos rf power-amplifier bias controller ____________________________________________________________________ 17 table 2 (pot1 temp lut) word 0 word 1 word 2 word 3 row (hex) row name byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 80 lut pot1 pot1 pot1 pot1 pot1 pot1 pot1 pot1 88 lut pot1 pot1 pot1 pot1 pot1 pot1 pot1 pot1 90 lut pot1 pot1 pot1 pot1 pot1 pot1 pot1 pot1 98 lut pot1 pot1 pot1 pot1 pot1 pot1 pot1 pot1 a0 lut pot1 pot1 pot1 pot1 pot1 pot1 pot1 pot1 a8 lut pot1 pot1 pot1 pot1 pot1 pot1 pot1 pot1 b0 lut pot1 pot1 pot1 pot1 pot1 pot1 pot1 pot1 b8 lut pot1 pot1 pot1 pot1 pot1 pot1 pot1 pot1 c0 lut pot1 pot1 pot1 pot1 pot1 pot1 pot1 pot1 c8 reserved reserved reserved reserved reserved reserved reserved reserved d0 reserved reserved reserved reserved reserved reserved reserved reserved d8 reserved reserved reserved reserved reserved reserved reserved reserved e0 reserved reserved reserved reserved reserved reserved reserved reserved e8 reserved reserved reserved reserved reserved reserved reserved reserved f0 reserved reserved reserved reserved reserved reserved reserved reserved f8 reserved reserved reserved reserved reserved reserved reserved reserved expanded bytes byte (hex) byte name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80-c7 pot1 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0
ds1870 ldmos rf power-amplifier bias controller 18 ____________________________________________________________________ table 3 ( pot2 temp lut) word 0 word 1 word 2 word 3 row (hex) row name byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 80 lut pot2 pot2 pot2 pot2 pot2 pot2 pot2 pot2 88 lut pot2 pot2 pot2 pot2 pot2 pot2 pot2 pot2 90 lut pot2 pot2 pot2 pot2 pot2 pot2 pot2 pot2 98 lut pot2 pot2 pot2 pot2 pot2 pot2 pot2 pot2 a0 lut pot2 pot2 pot2 pot2 pot2 pot2 pot2 pot2 a8 lut pot2 pot2 pot2 pot2 pot2 pot2 pot2 pot2 b0 lut pot2 pot2 pot2 pot2 pot2 pot2 pot2 pot2 b8 lut pot2 pot2 pot2 pot2 pot2 pot2 pot2 pot2 c0 lut pot2 pot2 pot2 pot2 pot2 pot2 pot2 pot2 c8 reserved reserved reserved reserved reserved reserved reserved reserved d0 reserved reserved reserved reserved reserved reserved reserved reserved d8 reserved reserved reserved reserved reserved reserved reserved reserved e0 reserved reserved reserved reserved reserved reserved reserved reserved e8 reserved reserved reserved reserved reserved reserved reserved reserved f0 reserved reserved reserved reserved reserved reserved reserved reserved f8 reserved reserved reserved reserved reserved reserved reserved reserved expanded bytes byte (hex) byte name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80-c7 pot2 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0
ds1870 ldmos rf power-amplifier bias controller ____________________________________________________________________ 19 table 4 ( pot1 drain lut) word 0 word 1 word 2 word 3 row (hex) row name byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 80 lut pot1 off pot1 off pot1 off pot1 off pot1 off pot1 off pot1 off pot1 off 88 lut pot1 off pot1 off pot1 off pot1 off pot1 off pot1 off pot1 off pot1 off 90 lut pot1 off pot1 off pot1 off pot1 off pot1 off pot1 off pot1 off pot1 off 98 lut pot1 off pot1 off pot1 off pot1 off pot1 off pot1 off pot1 off pot1 off a0 lut pot1 off pot1 off pot1 off pot1 off pot1 off pot1 off pot1 off pot1 off a8 lut pot1 off pot1 off pot1 off pot1 off pot1 off pot1 off pot1 off pot1 off b0 lut pot1 off pot1 off pot1 off pot1 off pot1 off pot1 off pot1 off pot1 off b8 lut pot1 off pot1 off pot1 off pot1 off pot1 off pot1 off pot1 off pot1 off expanded bytes byte (hex) byte name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80-bf pot1 off s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 table 5 (pot2 drain lut) word 0 word 1 word 2 word 3 row (hex) row name byte 0 byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 80 lut pot2 off pot2 off pot2 off pot2 off pot2 off pot2 off pot2 off pot2 off 88 lut pot2 off pot2 off pot2 off pot2 off pot2 off pot2 off pot2 off pot2 off 90 lut pot2 off pot2 off pot2 off pot2 off pot2 off pot2 off pot2 off pot2 off 98 lut pot2 off pot2 off pot2 off pot2 off pot2 off pot2 off pot2 off pot2 off a0 lut pot2 off pot2 off pot2 off pot2 off pot2 off pot2 off pot2 off pot2 off a8 lut pot2 off pot2 off pot2 off pot2 off pot2 off pot2 off pot2 off pot2 off b0 lut pot2 off pot2 off pot2 off pot2 off pot2 off pot2 off pot2 off pot2 off b8 lut pot2 off pot2 off pot2 off pot2 off pot2 off pot2 off pot2 off pot2 off expanded bytes byte (hex) byte name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80-bf pot2 off s 2 6 2 5 2 4 2 3 2 2 2 1 2 0
ds1870 ldmos rf power-amplifier bias controller 20 ____________________________________________________________________ register description the register descriptions are organized by the register? row address starting with the lower memory, then proceed- ing through each lookup table in order. the format of the register description is shown below. table name name of row name of byte < access >< volatility >< power-on/ factor default value s> description of the byte? function a) bit x bit x description b) bit y bit y description the access value following each byte? name defines the read/write access for the register. possible values are read-only (r), write-only (w), and read-write (r/w). the volatility parameter defines if the memory is volatile (v) or nonvolatile (nv). some registers correspond to values measured or detected by the ds1870. these parameters are read-only and listed as na since their values are indeterminate. power-on values are the default states of the volatile register, and the factory default values are the values the eeprom memory is programmed to by the factory before they are shipped from dallas semiconductor. lower memory user row user ee <00h> nv eeprom user memory. threshold 0 temp hi alarm <0000h> temperature measurements above this 2? complement threshold set its corresponding alarm bit. measurements below this threshold clear the alarm bit. v cc hi alarm <0000h> voltage measurements of the v cc input above this unsigned threshold set its corresponding alarm bit. measurements below this threshold clear the alarm bit. vd hi alarm <0000h> voltage measurements of the v d input above this unsigned threshold set its corresponding alarm bit. measurements below this threshold clear the alarm bit. id1 hi alarm <0000h> voltage measurements of the i d1 input above this unsigned threshold set its corresponding alarm bit. measurements below this threshold clear the alarm bit. threshold 1 id2 hi alarm < 0000h> voltage measurements of the i d2 input above this unsigned threshold set its corresponding alarm bit. measurements below this threshold clear the alarm bit. threshold 2 temp lo alarm < 0000h> temperature measurements below this 2? complement threshold set its corresponding alarm bit. measurements above this threshold clear the alarm bit. v cc lo alarm <0000h> voltage measurements of the v cc below above this unsigned threshold set its corresponding alarm bit. measurements above this threshold clear the alarm bit. vd lo alarm <0000h> voltage measurements of the v d input below this unsigned threshold set its corresponding alarm bit. measurements above this threshold clear the alarm bit. id1 lo alarm <0000h> voltage measurements of the i d1 input below this unsigned threshold set its corresponding alarm bit. measurements above this threshold clear the alarm bit. threshold 3 id1 lo alarm <0000h> voltage measurements of the i d2 input below this unsigned threshold set its corresponding alarm bit. measurements above this threshold clear the alarm bit.
ds1870 ldmos rf power-amplifier bias controller ____________________________________________________________________ 21 a2d value 0 temp value <0000h> the signed 2? complement direct-to-temperature measurement. v cc value <0000h> unsigned v cc voltage measurement. vd value <0000h> unsigned v d voltage measurement. id1 value <0000h> unsigned i d1 voltage measurement. a2d value 1 id2 value <0000h> unsigned i d2 voltage measurement. status hi alarm <00h> high-alarm status bits. a) temp hi high-alarm status for temperature measurement. b) v cc hi high-alarm status for v cc measurement. c) vd hi high-alarm status for v d measurement. d) id1 hi high-alarm status for i d1 measurement. e) id2 hi high-alarm status for i d2 measurement. lo alarm <40h> low-alarm status bits. a) temp lo low-alarm status for temperature measurement. b) v cc lo low-alarm status for v cc measurement. this bit is set when the v cc supply is below the por trip-point value. it clears itself when a v cc measurement is completed and the value is above the low threshold. c) vd lo low-alarm status for v d measurement. d) id1 lo low-alarm status for i d1 measurement. e) id2 lo low-alarm status for i d2 measurement. i/o status status of the fault pin. a) fault logical value of the fault pin. fault is logic high during power-on. b) mint maskable interrupt. fault is an open-drain output. in case fault was pulled low externally or was missing the external pullup resistor, this bit reflects the logical value the ds1870 is trying to output on the fault pin. if any ?i alarm?or ?o alarm?is active and its corresponding ?ault ena?bit is enabled, or ?dby?is a 1, then this bit is active high. otherwise, this bit is a zero. c) rdyb ready bar. when the supply is above the power-on-analog (v poa ) trip point, this bit is active low. thus, this bit reads a logic 1 if the supply is below v poa or too low to com- municate over the i 2 c bus. a2d status <00h> status of completed conversions. at power-on, these bits are cleared and are set as each conversion is completed. these bits can be cleared so that completion of new conversions may be verified. a) temp rdy temperature conversion is ready. b) v cc rdy v cc conversion is ready. c) vd rdy v d conversion is ready. d) id1 rdy i d1 conversion is ready. e) id2 rdy i d2 conversion is ready.
ds1870 ldmos rf power-amplifier bias controller 22 ____________________________________________________________________ pwe pwe password entry. until the correct password is written to this location, the only memory that can be written are addresses 78h to 7fh. this includes the pwe and table_select locations. all memory is readable regardless of the pwe value. tbl sel <00h> table select. the ds1870 contains four tables (1 to 5). writing a (1 to 5) value to this register grants access to the corresponding table. table 1 (configuration) config password the pwe value is compared against the value written to this location. all eeprom memory is write-protected when pwe does not match thisregister. lut sel <03h> selects which inputs are used to control the lookup tables. a) vd2 a one selects the v d input to control the drain lut indexing for pot2 (table 5). a zero selects the i d2 input. b) vd1 a one selects the v d input to control the drain lut indexing for pot1 (table 4). a zero selects the i d1 input. fault ena <00h> configures the maskable interrupt for the fault pin. a) temp ena temperature measurements, outside the threshold limits, are enabled to create an active interrupt on the fault pin. b) v cc ena v cc measurements, outside the threshold limits, are enabled to create an active interrupt on the fault pin. c) vd ena v d measurements, outside the threshold limits, are enabled to create an active interrupt on the fault pin. d) id1 ena i d1 measurements, outside the threshold limits, are enabled to create an active interrupt on the fault pin. e) id2 ena i d2 measurements, outside the threshold limits, are enabled to create an active interrupt on the fault pin. scale 0 v cc scale controls the scaling or gain of the v cc measurements. the v cc gain is factory trimmed to 6.5535v fs. vd scale controls the scaling or gain of the v d measurements. the v d gain is factory trimmed to 2.500v fs. id1 scale controls the scaling or gain of the i d1 measurements. the i d1 gain is factory trimmed to 0.5v fs. scale 1 id2 scale controls the scaling or gain of the i d2 measurements. the i d2 gain is factory trimmed to 0.5v fs. offset 0 v cc offset <0000h> allows for offset control of v cc measurement vd offset <0000h> allows for offset control of v d measurement. id1 offset <0000h> allows for offset control of i d1 measurement. offset 1 id2 offset <0000h> allows for offset control of i d2 measurement. temp offset <0000h> allows for offset control of temperature measurement. lut index
ds1870 ldmos rf power-amplifier bias controller ____________________________________________________________________ 23 t index <00h> holds the calculated index based on the temperature measurement. this index is used to address luts 2 and 3. o1 index <00h> holds the calculated index based on the v d or i d1 measurement (dependant on ?ut sel?byte). this index is used to address lut 4. o2 index <00h> holds the calculated index based on the v d or i d2 measurement (dependant on ?ut sel?byte). this index is used to address lut 5. pot1 base <00h> the base value used for pot1 and recalled from table 2 at the memory address found in ? index.?this register is updated at the end of the temperature conversion. pot1 is not updated with this value until the end of i d2 conversion to ensure that both the base and the offset are known for pot1 and pot2 and they are updated simultaneously. pot1 off <00h> the offset value used for pot1 and recalled from table 4 at the memory address found in ?1 index.?depending on the value written to ?ut sel?byte, this register is updated at the end of the v d or i d1 conversion. pot1 is not updated with this value until the end of i d2 conversion to ensure that both the base and the offset are known for pot1 and pot2 and they are updated simultaneously. pot2 base <00h> the base value used for pot2 and recalled from table 3 at the memory address found in ? index.?this register is updated at the end of the temperature conversion. pot2 is not updated with this value until the end of i d2 conversion to ensure that both the base and the offset are known for pot1 and pot2 and they are updated simultaneously. pot2 off <00h> the offset value used for pot2 and recalled from table 5 at the memory address found in ?2 index.?depending on the value written to ?ut sel?byte, this register is updated at the end of the v d or i d2 conversion. pot2 is not updated with this value until the end of i d2 conversion to ensure that both the base and the offset are known for pot1 and pot2 and they are updated simultaneously. man dac <03h> allows user to control either the lut index or the base and offset values used to calculate the potentiometer positions. a) see shadow ee bar. at power-on this bit is low, which enables ee writes to all shadowed ee locations. if written to a one, this bit allows for trimming and/or configuring the part without changing the nv-shadowed ee memory and not having to wait for the ee cycle time to complete. writing this bit to a zero does not cause a write from the sram to copy into the ee. shadow ee locations are addresses 20h to 3fh and table 180h to a7h. b) b/o_en at power-on this bit is high, which enables auto control of the lut. if this bit is written to a zero, then the pot base and offset are writeable by the user and the lut recalls are disabled. this allows the user to interactively test their modules by writing the base and/or offsets for the pots. the pots update with the new value at the end of the write cycle. thus, all four registers (?ot1 base,??ot1 off,??ot2 base,?and ?ot2 off? should be written in the same write cycle. the i 2 c stop condition is the end of the write cycle. c) index_en at power-on this bit is high, which enables auto control of the lut. if this bit is cleared to a zero, then the three index values (? index,??1 index,?and ?2 index? are write- able by the user and the updates of calculated indexes are disabled. this allows the user to interactively test their modules by controlling the indexing for the lookup tables. all three index values should be written in the same write cycle. the recalled values from the luts appear in the base and offset register after each corresponding conversion (just like it would happen in auto mode). to ensure the recalled base and offset values from the lut are updated, the base and offset calculation will not update the potentiometers until the completion of the next temperature and i d2 conversion. both pots update at the same time (just like it would happen in auto mode).
ds1870 ldmos rf power-amplifier bias controller 24 ____________________________________________________________________ i 2 c definitions the following terminology is commonly used to describe i 2 c data transfers. master device: the master device controls the slave devices on the bus. the master device generates scl clock pulses, and start and stop conditions. slave devices: slave devices send and receive data at the master? request. bus idle or not busy: time between stop and start conditions when both sda and scl are inactive and in their logic high states. when the bus is idle, it often initi- ates a low-power mode for slave devices. start condition: a start condition is generated by the master to initiate a new data transfer with a slave. transitioning sda from high to low while scl remains high generates a start condition. see the timing dia- gram for applicable timing. stop condition: a stop condition is generated by the master to end a data transfer with a slave. transitioning sda from low to high while scl remains high gener- ates a stop condition. see the timing diagram for applicable timing. repeated start condition: the master can use a repeated start condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. a repeated start condition is issued identically to a nor- mal start condition. see the timing diagram for applica- ble timing. bit write: transitions of sda must occur during the low state of scl. the data on sda must remain valid and unchanged during the entire high pulse of scl plus the sda scl t hd:sta t low t high t r t f t buf t hd:dat t su:dat repeated start t su:sta t hd:sta t su:sto t sp stop note: timing is referenced to v il(max) and v ih(min) . start figure 3. i 2 c timing diagram table 2 (temp lut for pot 1) bytes 80h?7h pot1 <00h>the unsigned base value for pot1. table 3 (temp lut for pot 2) bytes 80h?7h pot2 <00h>the unsigned base value for pot2. table 4 (drain lut for pot 1) bytes 80h?8h pot1 off <00h>the signed 2? complement offset value for pot1. table 5 (drain lut for pot 2) bytes 80h?8h pot2 off <00h>the signed 2? complement offset value for pot2.
ds1870 ldmos rf power-amplifier bias controller ____________________________________________________________________ 25 setup and hold time requirements (figure 3). data is shifted into the device during the rising edge of the scl. bit read: at the end a write operation, the master must release the sda bus line for the proper amount of setup time (figure 3) before the next rising edge of scl dur- ing a bit read. the device shifts out each bit of data on sda at the falling edge of the previous scl pulse and the data bit is valid at the rising edge of the current scl pulse. remember that the master generates all scl clock pulses, including when it is reading bits from the slave. acknowledgement (ack and nack): an acknowl- edgement (ack) or not acknowledge (nack) is always the 9th bit transmitted during a byte transfer. the device receiving data (the master during a read or the slave during a write operation) performs an ack by transmitting a zero during the 9th bit. a device per- forms a nack by transmitting a one during the 9th bit. timing (figure 3) for the ack and nack is identical to all other bit writes. an ack is the acknowledgment that the device is properly receiving data. a nack is used to terminate a read sequence or as an indication that the device is not receiving data. byte write: a byte write consists of 8 bits of information transferred from the master to the slave (most signifi- cant bit first) plus a 1-bit acknowledgement from the slave to the master. the 8 bits transmitted by the mas- ter are done according to the bit write definition and the acknowledgement is read using the bit read definition. byte read: a byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ack or nack from the master to the slave. the 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition above, and the master transmits an ack using the bit write definition to receive additional data bytes. the master must nack the last byte read to ter- minated communication so the slave will return control of sda to the master. slave address byte: each slave on the i 2 c bus responds to a slave addressing byte sent immediately following a start condition. the slave address byte (figure 4) contains the slave address in the most signifi- cant 7 bits and the r/ w bit in the least significant bit. the ds1870? slave address is 1010a 2 a 1 a 0 (binary), where a 2 , a 1 , and a 0 are the values of the address pins. the address pins allow the device to respond to one of eight possible slave addresses. by writing the correct slave address with r/ w = 0, the master indi- cates it will write data to the slave. if r/ w = 1, the mas- ter will read data from the slave. if an incorrect slave address is written, the ds1870 assumes the master is communicating with another i 2 c device and ignores the communications until the next start condition is sent. memory address: during an i 2 c write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. the memory address is always the second byte trans- mitted during a write operation following the slave address byte. i 2 c communication writing a single byte to a slave: the master must generate a start condition, write the slave address byte (r/ w = 0), write the memory address, write the byte of data, and generate a stop condition. remember the master must read the slave? acknowledgement during all byte write operations. writing multiple bytes to a slave: to write multiple bytes to a slave, the master generates a start condition, writes the slave address byte (r/ w = 0), writes the memory address, writes up to 8 data bytes, and gener- ates a stop condition. the ds1870 writes 1 to 8 bytes (1 page or row) with a single write transaction. this is internally controlled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent. the address counter limits the write to one 8-byte page (one row of the memory map). attempts to write to additional pages of memory without sending a stop condition between pages results in the address counter wrapping around to the beginning of the present row. example: a 3-byte write starts at address 06h and writes three data bytes (11h, 22h, and 33h) to three ?onsecutive?addresses. the result is that addresses 06h and 07h would contain 11h and 22h, respectively, and the third data byte, 33h, would be written to address 00h. to prevent address wrapping from occurring, the mas- ter must send a stop condition at the end of the page, then wait for the bus-free or eeprom-write time to elapse. then the master can generate a new start con- 1 010 a 2 a 1 a 0 7-bit slave address most significant bit determines read or write a 2 , a 1 , and a 0 pin values r/w figure 4. slave address byte
ds1870 ldmos rf power-amplifier bias controller 26 ____________________________________________________________________ dition, and write the slave address byte (r/ w = 0) and the first memory address of the next memory row before continuing to write data. acknowledge polling: any time an eeprom page is written, the ds1870 requires the eeprom write time (t w ) after the stop condition to write the contents of the page to eeprom. during the eeprom write time, the ds1870 will not acknowledge its slave address because it is busy. it is possible to take advantage of that phenomenon by repeatedly addressing the ds1870, which allows the next page to be written as soon as the ds1870 is ready to receive the data. the alternative to acknowledge polling is to wait for maxi- mum period of t w to elapse before attempting to write again to the ds1870. eeprom write cycles: when eeprom writes occur, the ds1870 writes the whole eeprom memory page, even if only a single byte on the page was modified. writes that do not modify all 8 bytes on the page are allowed and do not corrupt the remaining bytes of memory on the same page. because the whole page is written, bytes on the page that were not modified dur- ing the transaction are still subject to a write cycle. this can result in a whole page being worn out over time by writing a single byte repeatedly. writing a page one byte at a time wears the eeprom out eight times faster than writing the entire page at once. the ds1870? eeprom write cycles are specified in the nonvolatile memory characteristics table. the specification shown is at the worst-case temperature. it can handle approxi- mately 10x that many writes at room temperature. writing to sram-shadowed eeprom memory with see = 1 does not count as an eeprom write cycle when evaluating the eeprom? estimated lifetime. reading a single byte from a slave: unlike the write operation that uses the memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. to read a single byte from the slave, the master generates a start condition, writes the slave address byte with r/ w = 1, reads the data byte with a nack to indicate the end of the transfer, and generates a stop condition. manipulating the address counter for reads: a dummy write cycle can be used to force the address counter to a particular value. to do this, the master generates a start condition, writes the slave address byte (r/ w = 0), writes the memory address where it desires to read, gen- erates a repeated start condition, writes the slave address byte (r/ w = 1), reads data with ack or nack as applicable, and generates a stop condition. s p sr a n start 8 bits address or data repeated start stop ack not ack white boxes indicate the master is controlling sda shaded boxes indicate the slave is controlling sda write a single byte write up to an 8-byte page with a single transaction read a single byte with a dummy write cycle to move the address counter read multiple bytes with a dummy write cycle to move the address counter communications key s xx xx xx xx 1010 a 0 0 a memory address a data a p s 1010 0 a memory address a data a data a p s 1010 0 a memory address a sr 10 1 0 a 0 1 a data n p s 1010 0 a memory address a sr 10 1 0 1 a data a data a data a data n p notes: 1) all bytes are sent most significant bit first. 2) the first byte sent after a start condition is always the slave address, followed by the read/write bit. a 1 a 2 a 0 a 1 a 2 a 0 a 1 a 2 a 0 a 1 a 2 a 1 a 2 a 0 a 1 a 2 figure 5. i 2 c communications examples
ds1870 ldmos rf power-amplifier bias controller ____________________________________________________________________ 27 see figure 5 for a read example using the repeated start condition to specify the starting memory location. reading multiple bytes from a slave: the read opera- tion can be used to read multiple bytes with a single transfer. when reading bytes from the slave, the master simply acks the data byte if it desires to read another byte before terminating the transaction. after the master reads the last byte it nacks to indicate the end of the transfer and generates a stop condition. this can be done with or without modifying the address counter? location before the read cycle. the ds1870? address counter does not wrap on page boundaries during read operations, but the counter will roll from its upper most memory address ffh to 00h if the last memory location is read during the read transaction. application information power-supply decoupling to achieve best results, it is recommended that the power supply is decoupled with a 0.01? or a 0.1? capacitor. use high-quality, ceramic, surface-mount capacitors, and mount the capacitors as close as possible to the v cc and gnd pins to minimize lead inductance. sda scl a2 a1 a0 fault v cc gnd 5v 5v reference r pot1 r pot2 r s2 r s1 49.9k 4.22k rf power amp rf in rf out w 1 l 1 w 2 h com l 2 n.c. n.c. n.c. n.c. 4.7k 3 places 28v i d1 i d2 v d factory-calibrated 13-bit adc (customer adjustable full- scale and offset values) notes: 1) in this configuration, the voltage range of w 1 and w 2 is 3v-5v. this range can be extended using external resistors. 2) one max6156b can be used with multiple ds1870s. ds1870 max6165b typical operating circuit
ds1870 ldmos rf power-amplifier bias controller maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 28 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2006 maxim integrated products is a registered trademark of maxim integrated products, inc. is a registered trademark of dallas semiconductor corporation. sda and scl pullup resistors sda is an open-collector output on the ds1870 that requires a pullup resistor to realize high logic levels. a master using either an open-collector output with a pullup resistor or a push-pull output driver can be used for scl. pullup resistor values should be chosen to ensure that the rise and fall times listed in the ac elec- trical characteristics are within specification. advanced application a circuit showing the implementaion of current sensing using the ds1870 is shown under advanced application with current sense . sda scl a2 a1 a0 fault v cc gnd 5v 5v reference r pot1 49.9k (1%) low pass filter r pot2 r s2 r s1 4.22k (1%) vd id1 id2 rf power amp rf in rf out w 1 l 1 w 2 h com l 2 n.c. n.c. 4.7k 3 places notes: 1) in this configuration, the voltage range of w 1 and w 2 is 3v-5v. this range can be extended using external resistors. 2) one max6156b can be used with multiple ds1870s. ds1870 max6165b max4080 low pass filter max4080 28v advanced application with current sense chip information transistor count: 52,353 substrate connected to ground package information for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo .

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